Three-dimensional simulation and experimental study on the enhanced on/off current ratio in silicon nanowire field-effect transistors

Choi, Chang-Yong1; Jo, Yeong-Deuk1; Park, Joon-Sung1; Cho, Won-Ju1; Koo, Sang-Mo1; Li, Qiliang2; Edelstein, Monica D.2; Suehle, John S.2; Richter, Curt A.2; Vogel, Eric M.2 1Republic of Korea; 2United States

In this presentation, we report an approach based on three-dimensional numerical simulations for the investigation of the dependence of the on/off current ratio in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width. Due to their one dimensional structure, high surface-to-volume ratio, and small size, SiNWs devices have received considerable attention for use in integrated nanoscale electronics as well as high performance sensors. Recent experiments show that the on/off current ratio increases as the channel width of a top-down processed SiNWFET decreases. We utilize simple top-down test structures (i.e. the SiNW is fabricated via electron-beam lithography and etching of SOI substrates) based upon self-aligned Schottky-contacts that enable the electronic properties of SiNWs to be readily studied. The simultaneously prepared control FETs have also been characterized for comparison. In order to investigate the transport behavior in the devices with different channel geometries, we have performed detailed two-dimensional and three-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L and thickness t but varying channel widths L from 50 nm to 5 μm. By evaluating the potential distributions and current flow lines, we show that the electric field distributions close to the channel edges make the effective tunnel barrier lower for the on-current and higher for the off-current operation modes in SiNWFETs, which has been confirmed by the experimental characterization of the fabricated devices.

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