The development of new sub-micron technologies, i.e. advanced embedded logic & flash memory systems (90nm and below), requires complex solutions in terms of dry etching process.
In this paper it will be discussed the strategy to define, in typical high-density plasma, doped polysilicon floating-gate lines through a unique array-circuitry litho-mask and without 193nm photoresist. It will also be shown how the etching performance is strictly related to the underlying morphology (active area and field oxide), due to the intrinsic difference between circuitry and array zones and to the barc properties (conformal or not).
Because of the inability of 248nm photoresist to design small features on wafer, a high negative litho-etch CDbias is necessary to achieve the needed distance between the adjacent floating gate lines; a very polymerizing chemistry permits to reach this target but it could be dangerous in terms of poly residues in the circuitry zones (where polysilicon has to be completely removed). This issue becomes more critical if step between active area and field oxide (step-H) is different between array and circuitry and if the barc is not conformal.
It has been developed a etching strategy to compensate these serious issues avoiding to move to 193nm photoresist or double litho-mask (array & circuitry) and without to change the dimensional targets.
An extensive morphological analysis has been also performed to understand the correlation between step-H value and the etching performances: some interesting results describe clearly how, in presence of a not-conformal barc, the step-H could modulate: a) the CD pre & post etching; b) residual oxide thickness and uniformity; c) poly residues in circuitry d) barc and poly end-point time.
Finally It has been investigated the different etching behavior using a conformal barc comparing advantages and drawbacks respect to the previous approach.
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