|
One of the fundamental limits in the scaling of metal oxide semiconductor field-effect transistor (MOSFET) technology is the room-temperature (RT) limit of ~60 mV/decade in the inverse sub-threshold slope. We report on vertical integration of single surround-gated silicon nanowire field-effect transistors that operate as classical FETs and in a modified implementation as impact ionization FETs with inverse sub-threshold slopes below the room-temperature limit. The vertical surround gated field effect transistors were fabricated from epitaxially grown SiNWs on <111> Si substrates, where each transistor consists of a single nanowire, using PECVD deposited SiO2 as gate dielectric, Al gate and top contacts.
The classical FET implementation resulted in an ambipolar device behavior due to the Schottky contact formed on the drain electrode. An inverse sub-threshold slope of 250 mV/decade was measured which is attributed to the high interface state density of the gate dielectric.
In strong contrast, the modified FET device resulted in an inverse sub-threshold slope as low as 6 mV/decade at RT over four orders of magnitude in current. Here, the device operation is based on avalanche breakdown in a partially gated vertical nanowire.
The combination of impact ionization field effect transistors and vertical architecture is very promising for future low-power logic and ultra-high-density circuits.
|