Phosphorus δ-layers on Si(001) surfaces are an important model system in the context of nanoscale device fabrication using a scanning tunneling microscope (STM) [1-4]. By patterning a hydrogen resist layer on Si(001) with STM lithography, subsequent phosphine dosing, and Si encapsulation, robust planar nanostructures can be built [5-7]. The area where the nanoscale devices are patterned on the surface typically contains several monatomic steps. δ-layers are a convenient way to study to investigate aspects of electrical conduction in planar devices without the need for STM lithography. To study the influence of surface steps on the electronic transport properties, we present a combined study with STM and magnetotransport measurements on P δ-layers on Si(001) samples deliberately miscut 4° towards [110], which show a high density of surface steps [8]. The δ-layers were fabricated in ultra high vacuum on clean Si(001) surfaces. Phosphorus was incorporated into the surface by dosing with phosphine and subsequent annealing. The carrier density was varied between 2x1013 cm-2 and 1.7x1014 cm-2 by changing the phosphine dose. Thereafter the δ-layer was encapsulated with low temperature Si growth. Atomic-resolution STM was used to study all stages of the fabrication. We find that the P atoms are randomly distributed in the δ-layer. The samples were then fabricated into Hall bars and characterized by magnetotransport measurements at 4.2 K. We compare our results to studies on δ-layers fabricated on exactly oriented substrates [2,3] and discuss the implications of our results for nanoscale device fabrication using STM lithography.
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