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According to an urgent scaling down of CMOS process, a variety of alternative high-£e materials are being investigated as possible replacements for SiO2. However, a server charge trapping effect in high-£e materials is clearly conformed in many researches and development efforts. The charge trapping effect will significantly degrade the device performances and reliability. In our study, we systematically investigated the behavior of negative bias temperature instability (NBTI) of pMOSFETs with HfO2/SiON gate stack. We, for the first time, found that typical linear extrapolation does not work well for the lifetime extraction at normal operation condition since the polarity of dominant trapped charge in high-£e dielectrics is not the same at lower and higher stress voltage regimes. In other words, as the stress voltage is < -2V electron trapping dominates while hole trapping dominates when stress voltage is > -2V. Furthermore, the influences of elevated temperature on charge trapping effects in NBTI process were also studied. It demonstrated that the distinct behaviors of charge trapping/detrapping were observed for electrons and holes. Consequently, this anomalous NBTI phenomenon obviously contradicts the essence of the linear prediction in which the same degradation mechanism is assumed through the entire stress voltage range. |