The array of the square valleys on silicon surface is built by applying the process based on electron beam lithography . Through the plasma dry etching of silicon, the arrayed valleys sized of 240, 480, 720, 960 and 1200nm with the pitch of 600, 850, 1040, 1200, and 1400nm respectively are uniformly distributed on the surface of the silicon mesa. The mesa is 50µm x 100µm x 250nm. On its surface, aluminum of 330nm thick is deposited to form the metal semiconductor contact. Four contacts constitute the probing pads to measure the contact conductance (G). Each pad is with the area of 40x90(µm)2 and arranged in series with the distance of 20, 30, and 40µm. Compared with those have no valleys on silicon surface, a three-order improvement on G has been achieved.
The experimental results of N-silicon indicates that the normalized G with total valley area increases with the number of valley while decreases with its size. In addition, two annealing experiments are done from 20(20) to 575(625)°C with the annealing time of 10(1) minutes. For the temperature of 20, 200, 300, 350, 400, 450, 500, 550, 575, 600, and 625°C, the normalized G values are 2.78(2.78), 2.11(2.11), 1.02(2.11), 0.27(0.77), 0.31(0.12), 0.01(0.05), 0.03(0.07), 0.01(0.04), 1.24E-4(0.04), 0.04, and 8.28E-4 S/cm2 respectively. The profiles are quite flat from 20(20) to 550(600)°C, but above 550(600)°C , there is a dramatic drop of the normalized G . For the above experiments, all annealing is proceeded accumulatively on the same sample. Their results indicate that the contact can endure the temperature for thermal process up to 550°C.
Both 3-D SEM and AFM with high resolution are also taken to analyze the profile of the valley. It looks like a metal tip with the estimated depth of 25(160) nm for 480(1200)-nm valley. The profile of the valley and the result of the normalized G vs. the valley size indicate the cause of the high G can be attributed to the valleys function like a field emitter array. A further investigation with TEM is also on the way.
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