Low line-edge roughness (LER) in patterned and etched Si and SiGe thin films is important for several applications. LER affects light transmission in Si waveguides [1], reduces carrier mobility in FinFET devices [2] and increases leakage current in nanoscale MOSFETs [3]. Furthermore, sidewall roughness of poly-SiGe support material in the sidewall transfer lithography process [4,5] degrades the uniformity of the patterned nanowires [6].
LER in etched sidewalls is partially caused by the resist process as well as the etching itself. In this paper the effect of the commonly used HBr/Cl2 chemistry for dry etching on the LER of single crystalline Si, poly-Si and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by a sidewall AFM technique where the LER at different depths of the sidewall could be measured.
Thus a direct comparison between resist and the etched film LER could be made.
Samples were patterned by I-line lithography and etching was performed at RF power of 200 W using HBr/Cl2 (30/10 sccm) plasma. For single crystalline Si the resist and Si sidewalls had an LER of 1.3 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the resist sidewall roughness was increased to 2-3 nm due to light scattering from the rougher surface of the polycrystalline materials. The poly-Si film had a LER of 3-4 nm and the poly-SiGe film had a LER of 5-12 nm.
The results show that for single crystalline Si and poly-Si the sidewall roughness mainly originates from the resist. However, for poly-SiGe films the sidewall LER is considerably increased from that of the resist indicating that the dry etching is the main contributor to the LER. For applications requiring etched poly-SiGe films with an LER below 5 nm the etch parameters and/or chemistry should be optimized.
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[3] H.-W. Kim, et. al. IEEE Trans. Electron Devices 51, 1984 (2004).
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[5] Y.-K. Choi, et. al. IEEE Trans. Electron Devices 49, 436 (2002).
[6] Z. Zhang, et. al. Applied Physics Lett. 88, 043104 (2006). |