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Nowadays, the great challenge in materials science is the incorporation of complex systems in the area of the nano-technologies. A fundamental aspect is the production of materials with specific and controlled properties. Great parts of these materials are elaborated by aggregates of different components, in general of multilayer thin films. Generally, in these materials the interfaces define many of their properties. The photoemission spectroscopies play a preponderant role in the study of the electronic and compositional properties of solids. However, in standard laboratory conditions the reduce escape depth, added to low photon flux of conventional sources, make inaccessible depth profile information in a non-destructive way. In particular, the buried interfaces are not accessible for the great majority of the surface science non-destructive chemical, compositional and electronic techniques. An effective way to overcome this drawback is increasing the probing depth by detecting and analyzing electrons with a higher kinetic energy. Although, the effective attenuation length (EAL) in solids is material depending, its behavior is universal. Hence, electrons with 10 keV kinetic energy can reach EAL of 10 nm and in some cases, as GaAs, can reach 25 nm at 15 keV. This effect is indeed the one that gives its fundamental importance to Hard X-ray PhotoElectron Spectroscopy (HAXPES), making possible to obtain concentration, chemical and electronic depth profile in the tens nanometers scale. In this contribution, we will, first, present a brief description of the HAXPES and the Surface X-ray Diffraction (SXD) station at SpLine the Spanish CRG beamline at the ESRF. The experimental set-up incorporates a novel electron analyzer capable to detect electrons with kinetic energies between 10 eV and 15 KeV. The photon energy can also be varied between 7 and 45 keV. Secondly, we will present the results of the study by HAXPES and SXD of different multilayer stacks: once case will be dedicated to growth and thermal bulk diffusion of a thin Au layer of 25 nm over a Cu sample, the second example in related with the study on two buried interfaces on a CMOS Ge/Si/SiO2/HfO2/TiN stack, with thickness of 2500, 0.9, 0.5, 4 and 4 nm, respectively. |