Material issues of SiGe and Ge CMOS technologies
Claeys, Cor
Belgium

To keep track with Moore's law, strain engineering based on either a global or a local approach is gaining much interest and has already been successfully implemented for 65 and 45 nm technology nodes. Although the first goal is to improve the drive current by mobility enhancement, other performance parameters such as leakage current, carrier minority lifetime and low frequency 1/f noise have to be considered.
This presentation will first give an overview of the different strain engineering techniques already used or under investigated nowadays, before discussing more in detail their impact on several electrical device parameters. Attention will be given to illustrate a global approach based on strained Si on strain-relaxed SiGe buffer layers and the use of process-induced stressors such as an embedded SiGe layer and a contact etch stop etch layer (CESL) in a FinFET technology. Some advantages and disadvantages of the different approaches will be outlined. Finally, also the use of Ge and GeOI as high-mobility substrates is briefly addressed.
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